Various methods for generating a clock tree in such a manner as to satisfy various design rules are known in circuit design. For example, there is a technology for acquiring register information of a block having a change in floor planning and generating an optimal clock tree for each block based on the acquired information.
Moreover, if placement of cells such as a flip-flop (Flip Flop; FF) and a latch is modified after generation of a clock tree, the clock tree is modified with the modification of the placement of cells. In the following description, modifying the clock tree may be expressed as “redistributing the clock tree,” and similarly the modification of the clock tree as the “redistribution of the clock tree.”
An example of the above-mentioned technology for redistributing the clock tree is a known technology for redistributing the clock tree manually by the designer of the circuit.
Moreover, another example of the technology for redistributing the clock tree is a known technology for saving the clock tree already generated and changing the existing clock tree in the following manner if there is an additionally placed cell. In other words, such a known technology changes the existing clock tree by connecting a clock wire to the added cell as close as possible within the existing wiring of the clock net.    Patent Document 1: Japanese Laid-open Patent Publication No. 2000-057197    Patent Document 2: Japanese Laid-open Patent Publication No. 09-069119
However, in the above-mentioned known technologies for redistributing the clock tree, the clock tree is redistributed in such a manner as to satisfy various design rules. It is not easy to satisfy various design rules. Hence, the known technologies have a problem that the redistribution of the clock tree is difficult.